Keysight Technologies has announced a collaboration with Intel Foundry to support Integrated Multi-Die Interconnection Technology (EMIB-T), a advanced innovation aimed at improving high-performance packaging solutions for artificial intelligence (AI) and the markets of data centers in addition to the support of the Intel 18A process node.
The requirements of the workloads of the AI and the data center continue to grow in complexity, guaranteeing reliable communication between the chiplets and the 3Dics becomes more and more critical. High-speed data transfer and efficient power delivery are essential to meet performance requests for new generation semiconductor applications. The semiconductor industry takes up these challenges through emerging open standards, such as Universal Chiplet Interconnect Express ™ (UCIE ™) and a bunch of wires (ARC). These standards define interconnection protocols for chiplets and 3ques in advanced 2.5D / 3D or laminate / organic packages, allowing coherent and high quality integration on different design platforms.
By adopting these standards and checking the chiplets for compliance and the bond margin, Keysight EDA and Intel Foundry contribute to an increasing chiplet interoperability ecosystem. Collaboration aims to reduce development costs, mitigate risks and accelerate innovation in the design of semiconductors.
Chiplet Phy Designer by Keysight EDA, the latest solution for the design of high speed chiplet adapted to AI and data center applications, now offers advanced simulation capacities for the UCIE ™ 2.0 standard and introduces the support for the Bow Project Open Computer standard. As an advanced chiplet design at the system level and Die-to-Die design solution (D2D), Chiplet Phy Designer allows validation of the pre-Silicon level, rationalizing the path to the band.
Suk Lee, VP & GM of Ecosystem Technology Office, Intel Foundry
Our collaboration with Keysight EDA on EMIB-T Silicon Bridge Technology is a pivot step to advance high performance packaging solutions. By integrating standards like UCIE ™ 2.0, we improve flexibility in chiplet design for AI and data center applications, accelerating innovation and guaranteeing our customers new generation requests with precision.
Niels Fache, Vice-President and Managing Director, Keysight design software
Keysight EDA's Pioneer of Chiplet Physight EDA continues to redefine pre-Silicon validation, empowering chiplet designers with quick and precise verification. By proactively adopting evolutionary standards such as UCIE ™ 2.0 and Bow, and now with a critical support for the EMIB-T of Intel Foundry, we allow engineers to accelerate innovation and eliminate expensive design iterations before manufacturing.
